1. Field of the Invention
The present invention relates to a lithographic apparatus, and a method for manufacturing a device.
2. Background Art
A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., comprising part of, one, or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
In device manufacturing methods using lithographic apparatus, overlay is an important factor in the yield, i.e., the percentage of correctly manufactured devices. Overlay is the accuracy within which layers are printed in relation to layers that have previously been formed. The overlay error budget will often be 10 nm or less, and to achieve such accuracy, the substrate must be aligned to the mask pattern to be transferred with great accuracy. Any distortions, deformations or any other alignment errors can have a negative impact on overlay.
Errors of the type which may affect overlay tend to fall into two categories, intra field errors which are errors that occur within a single exposure field, and inter-field (or wafer grid) errors which are errors that occur when the tool steps from one field to the next.
In order to compensate for wafer deformation introduced by e.g., wafer processing (a thermal process can introduce stress in a wafer, which causes it to deform), it is sometimes desirable to perform Higher Order Wafer Alignment (HOWA) modeling. By measuring at multiple locations on the wafer, a HOWA model can be fitted, which follows the deformation. This fit determines what is called the wafer grid. Wafer grids determine the locations where many lithographic systems expose fields. As the type of wafer deformation mentioned above is an inter-field effect, HOWA models are applied to compensate for such inter-field effects. However, intra-field effects tend to distort inter-field wafer grids produced by the current polynomial based HOWA models.
This issue is exacerbated at the wafer edge. For example a 5th order polynomial HOWA model has 42 degrees of freedom; compared to just 6 for a commonly used linear 6 parameter model. At the wafer edge in particular; the density of measurements obtained for the model is less than for the center of the wafer, and the modeling accuracy at the wafer edge suffers accordingly. This issue, in combination with errors due to intra-field effects can result in overlay errors at the wafer edge of 5 nm or more.